A recent trend in communication transceivers in applications such as wireless LAN and cable-modem is to digitize multiple channels with a single Analog-to-Digital Converter. A multi-channel wireless LAN system requires Nyquist sampling of input frequencies above 70 MHz with effective number of bits in the order of 10-bits.
There are quite a few architectures which could be used to implement high-resolution (i.e., 10-bit or greater) ADCs. Pipeline architectures are known to use less power than the other architectures, but at the expense of conversion latency. In pipeline converters, power consumption can be optimized by an appropriate selection of bits per stage and capacitor scaling down the pipeline. Also, pipeline architectures are successfully implemented in CMOS using switched capacitor designs, which make them easy to integrate. Speed can be improved through the use of various parallel blocks through the pipeline.
A general block diagram of a state-of-the-art pipeline ADC is shown in FIG. 1. It consists of P low-resolution stages, delay elements synchronizing the stage outputs, and digital correction logic. Each stage has a resolution of Bi+ri bits, of which Bi represents the effective stage resolution and ri the redundancy for a comparator offset correction algorithm. Each stage digitizes the residue of the previous stage, so accordingly, the digital output B1 of the first stage contains the most significant bits (MSBs) while the output Bk of the last stage contains the least significant bits (LSBs). The stages operate concurrently; that is, at any time, the first stage operates on the most recent sample while all other stages operate on residues from previous samples. Serial stages operate in opposite clock phases.
FIG. 2A illustrates a block diagram for a first typical architecture for a residue stage of a typical prior art pipelined ADC 10. An input signal Vin is applied at input node 12. Within the stage, this node is connected to the input of a quantizer 14 and a (usually switched-capacitor) residue generator 16. The quantizer is typically an analog-to-digital converter such as a flash converter. The output of the quantizer 14 is a digital representation of the input signal, usually of only a few bits resolution. A DAC 18 in the residue stage generates a corresponding analog signal representing the quantizer output, and supplies this analog signal to a summer 22. At substantially the same time as the quantizer samples the analog input signal, in response to a clock signal applied at 24, a sample-and-hold (S/H) circuit 26 acquires and holds a sample of the input signal and supplies that held value to the summer 22. Summer 22 forms a difference signal representing the difference between the sampled input signal from the S/H circuit and the approximated input signal reproduction at the output of DAC 18. The resulting difference, or error, signal at 28 is preferably amplified by an amplifier 30 to scale the output residue signal at 32 to take advantage of the dynamic range of the next stage in the pipeline.
For each pipeline ADC stage, the accuracy of the residue generation (and, thus, of the whole converter) is highly dependent on the S/H circuit 23 and the quantizer 22 sampling the input signal at the same time. If there is too large a difference in the timing of those samples, then the residue signal ceases to represent the difference between the input signal at an instant and the ability of the quantizer and DAC to reproduce that input signal value. Hence the next stage will be presented with an error signal beyond its range of ability to correct for the initial conversion inaccuracy.
In order to provide a stable DC input for high-frequency signals, traditionally, most converters, including pipeline ADC's, make use of a dedicated front-end S/H circuit, between the input signal and node 12, as shown in FIG. 2B. S/H circuit 34 is clocked (i.e., takes its sample) half a clock cycle from S/H circuit 26 and quantizer 14. With this arrangement, input to the node 12 is not moving when it is sampled, so there is no risk that the quantizer and residue stage will sample different values of the waveform. In many implementations of the track-and-hold stage, a passive switched-capacitor sampling is utilized. A track-and-hold circuit adds noise at the signal input as well as consumes power. To account for the higher noise floor because of the noise injection due to the track and hold, the capacitors in the ADC stages have to be increased in size to reduce the thermal noise from these stages. This leads to a large increase in power consumption of the overall ADC.
Recently, ADC implementations without explicit S/H amplifiers have been demonstrated at the sub-50MSPS sampling rates. “A 55-mW, 10-bit 40-Msample/s Nyquist-Rate CMOS ADC,” IEEE J. of Solid-State Circuits, Vol. 35, No. 3, March 2000, of Mehr and Singer, also disclosed in U.S. Pat. No. 6,396,429 and “A 1.8V 14b 10MS/s Pipelined ADC in 0.18 um CMOS with 99 dB SFDR,” International Solid-State Circuits Conference, February 2004 of Chiu et. Al, are two such converters. However, both implementations do not satisfy the sampling rates requirements of many current applications.
Traditionally, an MDAC within a pipeline ADC stage is implemented using the switched capacitor (SC) technique, the core of the MDAC being essentially an SC integrator formed around an operational amplifier, or op-amp. A general unit capacitor MDAC of a Bi+r-bit pipeline stage is presented in FIG. 3 as a single-ended configuration for simplicity. The analysis below is based on the unit capacitor MDAC, but can be easily expanded for other MDAC topologies. The SC unit capacitor MDAC comprises 2Bi unit capacitors (Cs,0 . . . Cs,n−1 and Cf), switches that operate in the sample (φS) or hold (φH) phase, and an operational amplifier. During the sample phase φS, the bottom plates of all the unit capacitors (Cs,0 . . . Cs,n−1 and Cf), are connected to the stage input voltage Vin, i while the top plates of the capacitors are grounded through one switch. The so-called bottom-plate sampling can be employed by opening the common sampling switch to the ground in phase φS′, slightly before the input connecting switches in phase φS. After entering the hold phase φH, the bottom plate of the feedback capacitor Cf is connected to the operational amplifier output, while the sampling capacitors Cs,0 . . . Cs,n−1 are set to −Vref, 0, or +Vref depending on the output of the sub-ADC.
FIGS. 4, 5A and 5B illustrate the ADC design disclosed within U.S. Pat. No. 6,396,429 of Singer and Mehr, without an explicit S/H in front of Stage 1 of a pipeline ADC. In FIG. 4, an eight-stage pipelined converter based on the Singer and Mehr implementation, is shown. A first stage 62 has a quantizer 64 and a residue generator 66. This first stage samples the analog input signal Vin supplied at 68 and generates a residue signal at 70 for the next stage. There is no S/H interposed between the analog input signal and the first stage of the pipeline converter. However, a sampling operation is distributed inside first stage 62 to both the residue generator and the quantizer, as follows: An explicit sample and hold (S/H) 72 within the residue generator 66, and a flash converter 74, which provides the quantizer function, are connected in parallel to the input 68 and sample directly the input voltage Vin. More particularly, flash converter 74 includes a number (such as eight) comparators 76-1 through 76-n, each of which has an input connected to the input of the flash converter 74 via an explicit sample-and-hold (S/H) circuit 77. Singer and Mehr mention that alternatively, and preferably, the function of S/H 77 can be moved into each of the comparators 76-i, allowing the S/H 72 and the comparators 76-i inside the first stage 62 to sample directly the input voltage.
Within the circuit of FIG. 4, given the parallel sampling of the input signal on the MDAC and the quantizer, aperture errors, must be minimized in order to obtain good dynamic performance, particularly in the presence of high frequency signals input. This is achieved by matching the sampling networks for the (DAC) residue generator and the quantizer comparators in terms of topology and time constants.
An exemplary arrangement for the first stage 62 of an ADC according to the Singer and Mehr design is shown in FIG. 5A. Associated switch control signals are shown in FIG. 5B. The op-amp and switching network comprising residue generator 66 is shown on top of one out of the eight flash comparators 76-1, the other comparators being similarly configured and connected. During the tracking phase when φ1p is asserted, switches 92, 96, 98, 102 and 104 are closed and as signal φ2 is de-asserted, switches 94 and 106 are open; switch 108 is a single-pole, double throw switch thrown to the ground position when φ2 is asserted and to a reference voltage Vth1 otherwise. At the inverting input node to op-amp 116 there are connected one terminal each of switch 102, input sampling capacitor Cin, feedback capacitor Cf and reference capacitors Cr1 through Cr8. Each of the reference capacitors, such as capacitor Cr1, has another terminal connected to the pole of a single-pole, triple-throw switch 112; one throw is connected to a positive reference voltage, Vref+, one throw is connected to a negative reference voltage, Vref−, and one throw is connected to a common mode voltage, Vcm1. When φ1 is asserted, switch 112 is thrown to its middle position, connecting to the Vcm1 throw; when φ2 is asserted and the output D1 of the first comparator 76-1 is high, switch 112 is thrown to the Vref+ position; when φ2 is asserted and the output D1 of the first comparator 76-1 is low, switch 112 is thrown to the Vref− position. In the tracking phase, both capacitors Cin and each of Cinf1 through Cinf8 and are charged and track the input voltage. The sampling operation in the DAC occurs when switch 102 opens on the falling edge of φ1p. The sample is taken relative to common-mode voltage Vcm1 rather than around the op-amp 116. The sampling operation inside the flash comparators occurs on the same falling edge of φ1p when switch 104 opens. At this time, the comparator preamplifiers are also auto-zeroed. Separate reference capacitors (Cri in the DAC and Crfi in the flash converter, where i is an index variable) are required to accommodate the input common-mode range. The reference voltages for the comparators are sampled on the falling edge of φ1, as well. At this moment, the input voltage Vin is sampled and available on capacitors Cinfi, while corresponding reference voltages Vthi are sampled and available on Crfi. After the rising edge of φ2, the difference Vin-Vthi is sensed at the summing junction at the inverting inputs of the comparators. Meanwhile, the DAC transitions to the amplify phase (while φ2 is asserted) although the decision from the flash is not available yet. After a short delay Tdelay from the rising edge of the φ2 signal, which is necessary to allow the difference between the input and the references to be amplified inside the comparators, the latching signal Lat occurs and the comparator decision outputs D1-D8 become available to the DAC (after the latch 114 regenerates).
Considering now FIGS. 3 and 5A, it can be seen that compared to the traditional SC MDAC stage depicted in FIG. 3, in the Singer and Mehr implementation, the elimination of the dedicated S/H stage before the front stage requires an explicit input tracking capacitor Cin within the multiplying digital-to-analog converter (MDAC) stage, along with “replica” tracking switched capacitors for each comparator Cr1-Cr8. The presence of a dedicated input capacitor in the MDAC in addition reference capacitors leads to a large reduction of feedback factor of the MDAC opamp during the amplify phase. A reduced feedback factor MDAC opamp will limit the maximum sampling rate achievable and/or will burn extra power in the first stage.